Code Instruction Selection Based on SSA-Graphs

Instruction selection for embedded processors is a challenging problem. Embedded system architectures feature highly irregular instruction sets and complex data paths. Traditional code generation techniques have difficulties to fully utilize the features of such architectures and typically result in inefficient code. In this paper we describe an instruction selection technique that uses static single assignment graphs (SSA-graphs) as underlying data structure for selection. Patterns defined as graph grammar guide the instruction selection to find (nearly) optimal results. We present an approach which maps the pattern matching problem to a partitioned boolean quadratic optimization problem (PBQP). A linear PBQP solver computes optimal solutions for almost all nodes of a SSA-graph. We have implemented our approach in a production DSP compiler. Our experiments show that our approach achieves significant better results compared to classical tree matching.